`timescale 1ns / 100fs

module x4_test ;
  reg [3:0]  tdata = 7 ;
  wire [3:0] rdata ;
  reg b = 0 ;
  reg [31:0] temp ;

  always begin
     if ($stime < 2000) begin
       #0.3995 tdata <= tdata + 1 ;
       b = 1 ;
       end
     else if ($stime < 3000) begin
       #0.4008 tdata <= tdata + 1 ;
       b = 0 ;
       end
     else begin
       #0.3999 tdata <= tdata + 1 ;
       b = 1 ;
       end
  end

  initial begin
    $dumpvars(0) ;
    temp = $random ;
    $display ("random %h %h", temp, $random);
    $monitor ($stime, " noting where clock time changes with b = %b", b);
//    $monitor ($stime, " %b", rdata) ;
    #100 $finish ;
  end 

  reg [3:0] tdata_del ;

  sit_ver_x4_cdr dut (tdata, rdata) ;

  always @ (tdata)
    tdata_del <= #64.2 tdata ;
  always @ (tdata_del)
    #0.1 if (tdata_del != rdata) $display ("tdata_del/rdata diff", $stime);
  always @ (rdata)
    #0.1 if (tdata_del != rdata) $display ("tdata_del/rdata diff", $stime);

endmodule