//===========================================================================//
//
//  S Y N T H E Z I A B L E    miniUART   C O R E
//
//  www.OpenCores.Org - January 2000
//  This core adheres to the GNU public license  
//
// Design units   : miniUART core for the OCRP-1
//
// File name      : cbaf_uart_txunit.v (formerly TxUnit.vhd)
//
// Purpose        : Implements an miniUART device for communication purposes 
//                  between the OR1K processor and the Host computer through
//                  an RS-232 communication protocol.
//                  
//
//===========================================================================//
//
// Revision list
// Version   Author                 Date                        Changes
//
// 0.1      Ovidiu Lupas     15 January 2000                   New model
// 2.0      Ovidiu Lupas       17 April   2000    unnecessary variable removed
//  olupas@opencores.org
// 3.0      Chuck Benz       20 November 2005 Translate to verilog
//-----------------------------------------------------------------------------
// Description    : 
//-----------------------------------------------------------------------------
// Entity for the Tx Unit                                                    --
//-----------------------------------------------------------------------------
module cbaf_uart_txunit (/*AUTOARG*/
   // Outputs
   txd, trege, tbufe, 
   // Inputs
   clk, reset, enable, load, datao
   ) ;
   input	clk ;
   input 	reset ;
   input 	enable ;
   input 	load ;
   output 	txd ;
   output 	trege ; // Tx register empty
   output 	tbufe ; // Tx buffer empty
   input [7:0] 	datao ;
   
   reg 		txd, trege, tbufe ;
   reg [7:0] 	tbuff ;
   reg [7:0] 	treg ;
   reg [3:0] 	bitcnt ;

   always @ (posedge clk or negedge reset)
     if (~reset) begin
	trege <= 1 ;
	tbufe <= 1 ;
	txd <= 1 ;
	bitcnt <= 0;
     end
     else begin
	if (load == 1) begin
	   tbuff <= datao ;
	   tbufe <= 0 ;
	end

	if (enable == 1) begin
	   if ((tbufe == 0) && (trege == 1)) begin
	      treg <= tbuff ;
	      trege <= 0;
	      tbufe <= 1;
	   end

	   if (trege == 0)
	     case (bitcnt)
	       0: begin
		  txd <= 0 ;
		  bitcnt <= bitcnt + 1 ;
	       end // case: 0
	       9: begin
		  txd <= 1 ;
		  treg <= {1'b1, treg[7:1]} ;
		  bitcnt <= 0 ;
		  trege <= 1 ;
	       end // case: 9
	       default: begin
		  txd <= treg[0] ;
		  treg <= {1'b1, treg[7:1]} ;
		  bitcnt <= bitcnt + 1 ;
	       end
	     endcase
	end // if (enable == 1)
     end // else: !if(~reset)
   
endmodule