// Test chip for debug interface
//   assumes 100 MHz clock, serial in/out - that's it.


module cbaf_serdebug_demo 
  (
   input      clk100,
   input      resetl,

   // serial lines
   input      rxd,
   output     txd) ;

   wire [31:0] mem_address ;
   wire        mem_write ;
   wire [63:0] mem_wrdata ;
   wire        mem_read ;
   reg [63:0]  mem_rddata ;
   reg 	       mem_ack ;
   reg 	       clk33 ;
   reg [1:0]   div3 ;
   reg [63:0]  mem[0:511] ;

   always @ (posedge clk100 or negedge resetl)
     if (~resetl) begin
	div3 <= 0 ;
	clk33 <= 0 ;
     end
     else begin
	div3 <= (div3 == 2) ? 0 : div3 + 1 ;
	clk33 <= (div3 == 2) ;
     end
   
   always @ (posedge clk33)
     if (mem_write)
       mem[mem_address[8:0]] <= mem_wrdata ;
   
   always @ (posedge clk33 or negedge resetl)
     if (~resetl) begin
	mem_rddata <= 0 ;
	mem_ack <= 0 ;
     end
     else begin
	mem_ack <= mem_write || mem_read ;
	mem_rddata <= mem[mem_address[8:0]] ;
     end

   cbaf_serdebug serdbg
     (.txd		(txd),
      .clk33		(clk33),
      .resetl		(resetl),
      .rxd		(rxd),
      .mem_write	(mem_write),
      .mem_read		(mem_read),
      .mem_address	(mem_address),
      .mem_wrdata	(mem_wrdata),
      .mem_rddata	(mem_rddata),
      .mem_ack		(mem_ack)); 

endmodule